In a conventional continuous time sigma delta (CTSD) analog-to-digital converter (ADC), code transition glitches in the feedback DAC and intersymbol interference (ISI) may severely degrade accuracy. A scheme that makes a continuous time sigma delta ADC robust to ISI and DAC glitches has been described in U.S. Pat. No. 7,095,345, which is hereby incorporated by reference in its entirety. According to the described scheme, an input stages for a CTSD ADC may disconnect input resistors and a feedback DAC from integrators for a time period every clock cycle. During this time, the DAC may be updated with a new DAC input code. In this manner, errors from the DAC may not be propagated to the integrators. Further, disconnecting the DAC during this time may effectively implement a return to zero DAC, which may reduce ISI. However, disconnecting the DAC in this manner may also greatly reduce alias rejection, which is a desirable feature of conventional continuous time ADCs.
As illustrated in FIG. 1, conventional continuous time sigma delta ADC 100 may comprise a summing circuit 110, continuous time integrator 120, integrators 130, analog-to-digital converter (ADC) 140, and DAC 160. Summing circuit 110 may accept an analog input 105. The output of summing circuit 110 may be connected to the input of continuous time integrator 120. The output of continuous time integrator 120 may be connected to the input of integrators 130, which may be one or more integrators. Other integrators may be used in subsequent stages, and these other integrators may be continuous time integrators, or partly continuous time and partly switched capacitor in a hybrid implementation. The output of integrators 130 may be connected to the inputs of ADC 140, which may be a one-bit or multi-bit ADC that acts as a quantizer. The output of ADC 140 forms output 150 and also may be input into DAC 160. The output of DAC 160 may be connected to the negative input of summing circuit 110. The scheme illustrated within FIG. 1 may suffer from disadvantages. For example, sigma delta ADC 100 may suffer from poor linearity caused by glitches in the operation of the DAC and may include ISI, which may degrade performance.
FIG. 2 illustrates a continuous time integration scheme similar to that disclosed within U.S. Pat. No. 7,095,345, referenced above. A sigma delta modulator with a continuous time input stage 200 may comprise DAC 205, input resistors 217 and 219, switches 225, 230, and 235, capacitors 245 and 250, and amplifier 240. In the illustrated scheme, DAC 205 is disconnected using switches 225 and 235 before updating the input DAC code 210. DAC 205 is reconnected only upon being updated to a new code. While DAC 205 is disconnected, the input may be disconnected as well. This scheme may provide for increased jitter tolerance, smaller cap sizes and larger tuning range. A major drawback to this scheme is a reduction in antialiasing.
FIG. 3 illustrates timing diagram 300 associated with FIG. 2. Timing diagram 300 illustrates a master clock (MCLK) 310, INT_CLK 320, INT_CLKB 330, and DAC CODES 340. As illustrated, when INT_CLK 320 is high during time period T1 350, INT_CLKB 330 is low. During time period T2 360, a new DAC code may be input.
As discussed above, the scheme illustrated within FIG. 2 and FIG. 3 may result in reduced anti-aliasing. Standard continuous time sigma delta ADCs are well known to reject aliases of the signal bandwidth at multiples of the clock frequency, with alias rejection of more than 70 dB being possible. Disconnecting the input may be the equivalent to multiplying it by a square wave, which may be either zero or one. The square wave may be at the clock frequency and may contain all of its harmonics. Multiplying in the time domain corresponds to mixing in the frequency domain. Hence, the scheme illustrated within FIG. 2 may downconvert signals at all the harmonics of the clock frequency, losing most of the continuous time antialiasing benefits.
FIG. 4 shows the alias rejection, and degradation thereof, for the scheme described above in FIG. 2 at the clock frequency, two times the clock frequency and three times the clock frequency. The alias rejection is plotted against the ratio d of the interval the input stays disconnected and the modulator clock period, which may correspond to T2/(T1+T2), for example, with reference to FIG. 3.